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ultrafast, sige, open-collector hvds clock/data buffer adclk914 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features features 7.5 ghz operating frequency 7.5 ghz operating frequency 160 ps propagation delay 160 ps propagation delay 100 ps output rise/fall 100 ps output rise/fall 110 fs random jitter 110 fs random jitter on-chip input terminations on-chip input terminations extended industrial temperature range: ?40c to +125c extended industrial temperature range: ?40c to +125c 3.3 v power supply (v cc ? v ee ) 3.3 v power supply (v cc ? v ee ) applications applications clock and data signal restoration clock and data signal restoration high speed converter clocking high speed converter clocking broadband communications broadband communications cellular infrastructure cellular infrastructure high speed line receivers high speed line receivers ate and high performance instrumentation ate and high performance instrumentation level shifting level shifting threshold detection threshold detection functional block diagram functional block diagram d d q v cc v ee v t q d d q v cc v ee v t q v ref 06561-001 50? 50? 50? 50? adclk914 figure 1. general description the adclk914 is an ultrafast clock/data buffer fabricated on the analog devices, inc., proprietary, complementary bipolar (xfcb-3) silicon-germanium (sige) process. the adclk914 features high voltage differential signaling (hvds) outputs suitable for driving the latest analog devices high speed digital- to-analog converters (dacs). the adclk914 has a single, differential open-collector output. the adclk914 buffer operates up to 7.5 ghz with a 160 ps propagation delay and adds only 110 fs random jitter (rj). the input has a center tapped, 100 , on-chip termination resistor and accepts lvpecl, cml, cmos, lvttl, or lvds (ac-coupled only). a v ref pin is available for biasing ac-coupled inputs. the hvds output stage is designed to directly drive 1.9 v each side into 50 terminated to v cc for a total differential output swing of 3.8 v. the adclk914 is available in a 16-lead lfcsp. it is specified for operation over the extended industrial temperature range of ?40c to +125c.
adclk914 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ..............................................7 applications information .................................................................9 power/ground layout and bypassing ........................................9 hvds output stage ......................................................................9 interfacing to high speed dacs .................................................9 optimizing high speed performance ........................................9 random jitter .................................................................................9 typical application circuits ..................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 10/08rev. 0 to rev. a changes to input low voltage parameter, table 1 ....................... 3 changes to output high voltage parameter, table 1 ................ 3 changes to output low voltage parameter, table 1 .................. 3 output differential range parameter, table 1 ............................ 3 changes to absolute maximum ratings section ........................ 5 7/08revision 0: initial version
adclk914 rev. a | page 3 of 12 specifications electrical characteristics v cc = 3.3 v, v ee = 0 v, t a = ?40c to +125c. all outputs terminated through 50 to v cc , unless otherwise noted. table 1. parameter symbol min typ max unit test conditions/comments dc input characteristics input high voltage v ih v ee + 1.65 v cc v input low voltage v il v ee v cc ? 0.2 v input differential range v id 0.2 3.4 v p-p t a = ?40c to +85c (1.7 v between input pins) 0.2 2.8 v p-p t a = 85c to 125c (1.4 v between input pins) input capacitance c in 0.4 pf input resistance 50 differential mode 100 common mode 50 k open termination input bias current 20 a dc output characteristics output high voltage v oh v cc ? 0.55 v cc ? 0.40 v cc ? 0.25 v output low voltage v ol v cc ? 2.75 v cc ? 2.35 v cc ? 1.9 v output differential range v od 1.54 1.95 2.22 v reference voltage v ref output voltage (v cc + 1)/2 v ?500 a to +500 a output resistance 250 ac performance operating frequency 7.5 ghz >1.1 v differential output swing, v cc = 3.3 v 10% propagation delay t pd 127 158 202 ps v cc = 3.3 v 10%,v icm = v ref , v id = 1.6 v p-p propagation delay temperature coefficient 140 fs/c propagation delay skew (device to device) 65 ps v id = 1.6 v p-p output rise time t r 100 125 ps 20%/80% output fall time t f 80 95 ps 80%/20% wideband random jitter 1 rj 110 fs rms v id = 1.6 v p-p, 6 v/ns, v icm = 1.85 v additive phase noise 622.08 mhz ?132 dbc/hz @10 hz offset ?143 dbc/hz @100 hz offset ?151 dbc/hz @1 khz offset ?156 dbc/hz @10 khz offset ?157 dbc/hz @100 khz offset ?156 dbc/hz >1 mhz offset 245.76 mhz ?133 dbc/hz @10 hz offset ?143 dbc/hz @100 hz offset ?153 dbc/hz @1 khz offset ?158 dbc/hz @10 khz offset ?159 dbc/hz @100 khz offset ?158 dbc/hz >1 mhz offset
adclk914 rev. a | page 4 of 12 parameter symbol min typ max unit test conditions/comments 122.88 mhz ?150 dbc/hz @10 hz offset ?156 dbc/hz @100 hz offset ?160 dbc/hz @1 khz offset ?161 dbc/hz @10 khz offset ?161 dbc/hz @100 khz offset ?160 dbc/hz >1 mhz offset power supply supply voltage requirement v cc 2.97 3.63 v power supply current negative supply current i vee 66 111 150 ma includes output current positive supply current i vcc 34 55 73 ma power supply rejection 2 psr vcc 13 ps/v v cc = 3.3 v 10% output swing supply rejection 3 ?15 db v cc = 3.3 v 10% 1 calculated from snr of adc method. see figure 8 for rms jitter vs. input slew rate. 2 change in t pd per change in v cc . 3 change in output sw ing per change in v cc .
adclk914 rev. a | page 5 of 12 absolute maximum ratings table 2. parameter rating supply voltage (v cc to gnd) 6.0 v input voltage ?0.5 v to v cc + 0.5 v maximum output voltage v cc + 0.5 v minimum output voltage v ee ? 0.5 v input termination 2 v voltage reference v cc ? v ee operating temperature range, ambient ?40c to +125c operating temperature, junction 150c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal performance the adclk914 is specified for a case temperature (t case ). to ensure that t case is not exceeded, use an airflow source. to determine the junction temperature on the application pcb t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the customer at top center of package. jt is determined by the values listed in table 3 . pd is the power dissipation. va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). values of jb are provided for package comparison and pcb design considerations. table 3. thermal parameters for adclk914 16-lead lfcsp symbol description 1 value units ja junction-to-ambient thermal resistance, 0.0 meters per sec air flow per jedec jesd51-2 (still air) 78.4 c/w jma junction-to-ambient thermal resistance, 1.0 meter per sec air flow per jedec jesd51-6 (moving air) 68.5 c/w jma junction-to-ambient thermal resistance, 2.5 m/s air flow per jedec jesd51-6 (moving air) 61.4 c/w jb junction-to-board thermal resistance, 1.0 meter per sec air flow per jedec jesd51-8 (moving air) 48.8 c/w jc junction-to-case thermal resistance (die-to-heatsink) per mil-std 883, method 1012.1 1.5 c/w jt junction-to-top-of-package characterization parameter, 0 meters per sec air flow per jedec jesd51-2 (still air) 2.0 c/w 1 descriptions based on using a 2s2p test board. esd caution
adclk914 rev. a | page 6 of 12 pin configuration and fu nction descriptions pin 1 indicator nc = no connect 1d 2d 3 nc 4 nc 11 12 10 9 5 n c 6 n c 7 v e e 8 v c c 1 5 v r e f 1 6 v t 1 4 v e e 1 3 v c c adclk914 top view (not to scale) 06561-002 q q nc nc figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 d noninverting input. 2 d inverting input. 3, 4, 5, 6, 9, 10 nc no connect. no physical connection to the die. 7, 14 v ee negative supply voltage. 8, 13 v cc positive supply voltage. 11 q inverting output. 12 q noninverting output. 15 v ref reference voltage. reference voltage for biasing ac-coupled inputs. 16 v t center tap. center tap of 100 input resistor. heat sink/ exposed pad nc no connect. the metallic back surface of the package is not electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to ground on the ap plication board if improved thermal and/or mechanical stability is needed. exposed metal at the corners of th e package is connected to this back surface. allow sufficient clearance for vias and other components.
adclk914 rev. a | page 7 of 12 typical performance characteristics v cc = 3.3 v, v ee = 0 v, t a = 25c. all outputs terminated through 50 to v cc , unless otherwise noted. 06561-003 q q 250mv/di v 62.5ps/div figure 3. output waveform at 1 ghz, v cc = 3.3 v ? 120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) 06561-004 figure 4. phase noise at 122.88 mhz ? 120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) 06561-005 figure 5. phase noise at 245.76 mhz 06561-006 q q 250mv/di v 100ps/div figure 6. output waveform at 1 ghz, v cc = 3.3 v ? 120 ?130 ?140 ?150 ?160 ?170 10 100 1k 10k 100k 1m 10m 100m frequency (hz) phase noise (dbc/hz) 06561-007 figure 7. phase noise at 622.08 mhz 350 0 012345678 input slew rate (v/ns) rms jitter (fs) 06561-008 300 250 200 150 100 50 t a = 25c figure 8. rms jitter vs. input slew rate
adclk914 rev. a | page 8 of 12 3.80 3.75 3.70 3.65 3.60 3.55 3.50 2.97 3.13 3.30 3.46 3.63 power supply voltage (v) differential output swing (v) 06561-009 figure 9. differential output swing vs. power supply voltage 115 114 113 112 111 110 109 108 107 106 105 2.97 3.13 3.30 3.46 3.63 power supply voltage (v) power supply current (ma) 06561-010 figure 10. power supply curren t vs. power supply voltage 200 180 160 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 input common mode (v) propagation delay (ps) 06561-011 figure 11. propagation delay vs. v icm ; v id = 1.6 v p-p 162 160 158 156 154 152 150 148 146 0.4 0.8 1.2 1.6 2.0 input differential (v p-p) propagation delay (ps) 06561-012 figure 12. propagation delay vs. v id ; v icm = 2.15 v 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 frequency (ghz) differential output swing (v) 06561-013 figure 13. toggle rate, different ial output swing vs. frequency
adclk914 rev. a | page 9 of 12 applications information power/ground layout and bypassing the adclk914 buffer is designed for very high speed applica- tions. consequently, high speed design techniques must be used to achieve the specified performance. it is critically important to use low impedance supply planes for both the negative supply (v ee ) and the positive supply (v cc ) planes as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. place a 1 f electrolytic bypass capacitor within several inches of each power supply pin to ground. in addition, place multiple high quality 0.001 f bypass capacitors as close as possible to each v ee and v cc supply pin and connect these cap- acitors to the gnd plane with redundant vias. carefully select high frequency bypass capacitors for minimum inductance and esr. to maximize the effectiveness of the bypass capacitors at high frequencies, strictly avoid parasitic layout inductance. slew currents may also appear at the v dd and v ss pins of the device being driven by the adclk914. hvds output stage the adclk914 has been developed to provide a bipolar interface to any cmos device that requires extremely low jitter, high amplitude clocks. it is intended to be placed as close as possible to the receiving device and allows the rest of the clock distribu- tion to run at standard cml or pecl levels. interconnects must be short and very carefully designed because the single terminated design provides much less margin for error than lower voltage, double terminated transmission techniques. 06561-015 v ee q q 40ma v ee 7ma v ee 7ma figure 14. simplified schematic diagram of the adclk914 hvds output stage interfacing to high speed dacs the adclk914 is designed to drive high amplitude, low jitter clock signals into high speed, multi-gsps dacs. the adclk914 should be placed as close as possible to the clock input of the dac so that the high slew rate and high amplitude clock signal that these devices require do not cause routing difficulties, generate emi, or become degraded by dielectric and other losses. the adclk914, in turn, may be driven directly by standard or low swing pecl, cml, cmos, or lvttl sources, or by lvds with simple ac coupling, as illustrated in figure 15 through figure 19 . optimizing high speed performance as with any high speed circuit, proper design and layout tech- niques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power, and ground impedances, as well as other layout issues, can severely limit performance and can cause oscillation. discontinuities along input and output transmission lines can also severely limit the specified jitter performance by reducing the effective input slew rate. input and output matching have a significant impact on performance. the adclk914 buffer provides internal 50 termination resistors for both d and d inputs. the return side can be connected to the reference pin provided or to a current sink at v cc ? 2 v for use with differential pecl, or to v cc for direct coupled cml. the v ref pin should be left floating any time that it is not used to minimize power consumption. note that the adclk914 v ref source is current-limited to resist damage from momentary shorts to v ee or v cc and from capacitor charging currents; for this reason, the v ref source cannot be used as a pecl termination supply. carefully bypass the termination potential using ceramic capa- citors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. if the inputs are directly coupled to a source, care must be taken to ensure that the pins remain within the rated input differential and common-mode ranges. if the return is floated, the device exhibits 100 cross-term- ination, but the source must then control the common-mode voltage and supply the input bias currents. esd/clamp diodes between the input pins prevent the appli- cation of excessive offsets to the input transistors. esd diodes are not optimized for best ac performance. if a clamp is needed, it is recommended that appropriate external diodes be used. random jitter the adclk914 buffer has been specifically designed to minimize random jitter over a wide input range. provided that sufficient voltage swing is present, random jitter is affected most by the slew rate of the input signal. whenever possible, clamp excessively large input signals with fast schottky diodes because attenuators reduce the slew rate. input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics.
adclk914 rev. a | page 10 of 12 typical application circuits v ref v cc v t d d connect v t to v cc . 06561-017 figure 15. interfacing to cml inputs v ref v t d d notes 1. placing a bypass capacitor from v t to ground can improve the noise performance. connect v t to v ref . 06561-019 figure 16. ac coupling differential signals v ee 40ma v ee 7ma v ee 7ma q q v cc 06561-021 figure 17. interfacing to high speed dac v ref v cc ? 2v v t d d connect v t to v cc ? 2v. 06561-018 figure 18. interfacing to ecl inputs v ref v t d d connect v t , v ref , and d. place a bypass capacitor from v t to ground. alternatively, v t , v ref , and d can be connected, giving a cleaner layout and a 180o phase shift. 06561-020 figure 19. interfacing to ac-c oupled, single-ended inputs
adclk914 rev. a | page 11 of 12 * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 3.00 bsc sq 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad bottom view 071708-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 20. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters ordering guide model temperature range packag e description package option adclk914bcpz-wp 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-3 ADCLK914BCPZ-R7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-3 adclk914bcpz-r2 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-3 adclk914/pcbz 1 evaluation board 1 z = rohs compliant part.
adclk914 rev. a | page 12 of 12 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06561-0-10/08(a)

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